SDI Signals

SDI signals are generally immune to the causes of disruption that damage their analog predecessors. Minor level fluctuations, common mode interference, signal polarity and induced hum have little or no effect on the receiveability of SDI signals. However, jitter induced by transmission lines or clock instability can cause errors at the receiver that vary from occasional bit errors (pixel drop-outs or sparkles) to complete reception failure.

Care should be taken to avoid transmission line jitter by ensuring that good quality coaxial cables are selected, that lengths are kept within manufacturers' recommendations and that patch bays and terminations are of the correct impedance. There are still some patch bays and terminators sold for video applications that have a nominal impedance of 50 ohms. If used they may induce jitter that is only apparent in certain paths, due to the accumulation of transmission line and clock jitter. It may be very difficult to identify the source of the problem.

When the serial digital interface was developed, it was necessary to scramble the data to remove the possibility of recurring data patterns of 1s or 0s that could potentially cause a temporary shift in the DC level. If a significant DC shift occurred it could reduce the receiver's ability to recover the signal data. To overcome this, a nine-bit polynomial filter was included in the serializer design. At that time a video sample was eight bits deep, and so the signal could be effectively scrambled to remove any repetitive patterns.

When the sample depth was changed to 10 bits, two specific combinations of luma and chroma values caused the nine-bit scrambler to generate a string of a 1 and 19 0s, or 2 1s and 18 0s. These two are referred to as pathological values. As these samples would theoretically need to be repeated consistently to cause a significant DC shift, the SDI standards were left unchanged. In most situations, repeated pathological samples should not result in errors, however, a poorly designed receiver may translate these signals into visible bit errors or "sparkles". (EQ Stress and PLL Stress are pathological test signals. Check Field is a split field test signal with half a field of EQ stress followed by half a field of PLL stress.)

The SDI data stream is NRZI (Non Return to Zero Inverting) coded. NRZI coding provides circuit designers with the ability to use both positive and negative outputs of the differential amplifiers in circuit designs, which significantly reduces component count and therefore product costs. It is not normal practice to identify which paths within a design invert a signal.

The HD-SDI and HD-SDTI are basically much higher bandwidth versions of SDI and SDTI, The bit rates are much faster (1.5 Gbits) and therefore need to be handled with much greater care than the standard definition counterpart.

Clock stability, transmission line impedance and return losses become far more critical at HD-SDI data rates. Cable type and length, the quality of physical termination (how accurately the BNC is attached), and the choice of patch bays and terminators are all critical factors in creating an error-free system. At 1.5 Gbit/s, small cable stubs and short unshielded conductors can become large reflectors and a source of error-inducing jitter. Poor return loss in a receiver design can reflect back into the transmitting device, generating show-stopping errors.

Jitter is the most common cause of bit errors in the HDSDI system, and not all products are equal in their ability to minimize or overcome these errors. SMPTE 292M specifies that output jitter should not exceed 134 ps. Our tests of various HD-SDI origination devices have revealed that many currently available products generate a level of jitter that is not always within SMPTE 292M specifications. If these signals accumulate small amounts of additional jitter in the transport path, bit errors will likely result.

It has been discovered that most output designs that include dual or multiple outputs can exhibit increased jitter levels if unused outputs are not terminated. These unused outputs can easily become a source of reflections that will feed back into the output amplifier unless it is correctly loaded.

Reclocking requires the use of a phase locked loop (PLL) with an accurate oscillator. At 1.5 Gbit/s, designing an oscillator with a sufficiently low jitter level is quite difficult (there is always some level of clock instability at any frequency). Minimizing clock jitter is the key to designing an effective reclocker. Again, not all designs are equal. Modern PLL designs generate minimum clock jitter. This ensures that reclocking devices provide the functionality required for the application.